IDT74ALVCH16832

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

This 1-bit to 4-bit address register/driver of the IDT74ALVCH16832  is built using advanced dual metal CMOS technology. This device is ideal for use in applications in which a single address bus is driving four separate memory locations. The ALVCH16832 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE) controls. Each OE controls two groups of seven outputs. When SEL is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode.

The IDT74ALVCH16832 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The IDT74ALVCH16832 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.