Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• VCC = 2.5V ± 0.2V...
IDT74ALVCH16345: Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)•...
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Description |
Symbol |
Max |
unit |
Terminal Voltage with Respect to GND |
VTERM(2) |
0.5 to +4.6
|
V |
Terminal Voltage with Respect to GND |
VTERM(3)
|
0.5 to VCC+0.5 |
V |
Storage Temperature |
TSTG |
65 to +150
|
° C |
DC Output Current |
IOUT
|
50 to +50 |
mA |
Continuous Clamp Current, VI < 0 or VI > VCC |
IIK |
±50
|
mA |
Continuous Clamp Current, VO < 0 |
IOK |
50 |
mA |
Continuous Current through each VCC or GND |
ICC ISS |
±100 |
mA |
This registered address line driver of the IDT74ALVCH16345 is built using advanced dual metal CMOS technology. The ALVCH16345 is configured with banks of four drivers, each to be used in high speed synchronous memory applications. The ALVCH16345 is ideal for driving memory modules in systems where multiple memory modules are used. One each of the four output banks drives a different module; modules can be added or removed without affecting the signal integrity of the other modules in the system.
Dual clock enables (CEx) of the IDT74ALVCH16345 allow use of the device in high speed memory interleaving applications where the clock can be alternately enabled and disabled, allowing the address to be held for additional cycles during memory access.
The IDT74ALVCH16345 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The IDT74ALVCH16345 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.