IDT74ALVCH16271

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

The IDT74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs high-speed microprocessors.

A data of the IDT74ALVCH16271 is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA) inputs low. Proper control of these inputs allows two sequential 12-bit words to presented as a 24-bit word on the B port. Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE) inputs are low.

The select (SEL) line of the IDT74ALVCH16271 selects 1B or 2B data for the A inputs. Data flow is controlled by the activelow output enables (OEA, OEB). The ALVCH16271 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16271 has "bus-hold" which retains the inputs' last state whenever