Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• VCC = 2.5V ± 0.2V...
IDT74ALVCH162260: Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)•...
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Symbol |
Rating |
Max
|
Unit |
VTERM (VDD) |
VDD Terminal Voltage with Respect to GND |
0.5 to +4.6 |
V |
VTERM(2) |
VDDQ Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
VTERM(2) (INPUTS and I/O's) |
Input and I/O Terminal Voltage with Respect to GND |
65 to +150
|
°C |
IOUT |
DC Output Current |
50 to +50
|
°C |
TSTG |
Continuous Clamp Current, VI < 0 or VI > VCC |
-65 to +150
|
mA |
TJN |
Junction Temperature |
+ 150
|
mA |
IOK |
Continuous Clamp Current, VO < 0 |
-50
|
mA |
ICC ISS |
Continuous Current through VCC or GND |
±100
|
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
This multiplexed D-type latch of the IDT74ALVCH162260 is built using advanced dual metal CMOS technology. The ALVCH162260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications. Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals of the IDT74ALVCH162260 also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The IDT74ALVCH162260 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The "A" port has a ± 24mA driver. The IDT74ALVCH162260 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.