Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• VCC = 2.5V ± 0.2V...
IDT74ALVCF162835A: Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)•...
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Symbol |
Description |
Max |
Unit |
VTERM(2) |
Terminal Voltage with Respect to GND |
0.5 to +4.6 |
V |
VTERM(3) |
Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
TSTG |
Storage Temperature |
65 to +150 |
|
IOUT |
DC Output Current |
50 to +50 |
mA |
IIK |
Continuous Clamp Current, VI < 0 or VI > VCC |
±50 |
mA |
IOK |
Continuous Clamp Current, VO < 0 |
50 |
mA |
ICC ISS |
Continuous Current through each VCC or GND |
±100 |
mA |
This 18-bit universal bus driver of the IDT74ALVCF162835A is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state.
The IDT74ALVCF162835A has series resistors in the device output structure which will reduce switching noise in 128MB and 256MB SDRAM modules.Designed with a drive capability of ±18mA, the ALVCF162835A is a midway drive between the ALVC162835 (±12mA) and ALVC16835 (±24mA).
The IDT74ALVCF162835A is a faster version of the ALVCF162835 or ALVC162835. It is suitable for PC133 applications and particularly SDRAM Modules clocked at 133 MHz.