IDT74ALVC16841

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

This 20-bit bus-interface D-type latch of the IDT74ALVC16841 is built using advanced dual metal CMOS technology. The ALVC16841 features 3-state outputs designed specifically for driving highly capacitive relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers. The ALVC16841 can be used as two 10-bit latches or one 20-bit latch.

The 20 latches of the IDT74ALVC16841 are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE or 2OE) input of the IDT74ALVC16841 can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The IDT74ALVC16841 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.