IDT74ALVC16260

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

This 12-bit to 24-bit multiplexed D-type latch of the IDT74ALVC16260 is built using advanced dual metal CMOS technology. The ALVC16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications.

This IDT74ALVC16260 also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE2B, OE2B, and OEA) inputs control the bus transceiver functions. The OE2B and OE2B control signals also allow bank control in the A-to-B direction. Address and/ or data information can be stored using the internal storage latches.

The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs of the IDT74ALVC16260 are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVC16260 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.