Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• VCC = 2.5V ± 0.2V...
IDT74ALVC162268: Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)•...
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Symbol |
Rating |
Max
|
Unit |
VTERM (VDD) |
VDD Terminal Voltage with Respect to GND |
0.5 to +4.6 |
V |
VTERM(2) |
VDDQ Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
VTERM(2) (INPUTS and I/O's) |
Input and I/O Terminal Voltage with Respect to GND |
65 to +150
|
°C |
IOUT |
DC Output Current |
50 to +50
|
°C |
TSTG |
Continuous Clamp Current, VI < 0 or VI > VCC |
-65 to +150
|
mA |
TJN |
Junction Temperature |
+ 150
|
mA |
IOK |
Continuous Clamp Current, VO < 0 |
-50
|
mA |
ICC ISS |
Continuous Current through VCC or GND |
±100
|
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
This registered bus exchanger of the IDT74ALVC162268 is built using advanced dual metal CMOS technology. This device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus.
The IDT74ALVC162268 device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-tohigh transition of the clock (CLK) input when the appropriate clock-enable CLKEN) inputs are low.
The select (SEL) line of the IDT74ALVC162268 is synchronous with CLK and selects 1B or 2B input data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24- bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB).
These control terminals of the IDT74ALVC162268 are registered to synchronize the bus-direction changes with CLK. The ALVC162268 has series resistors in the device output structure of the "B" port which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The "A" port has a ±24mA driver.