IDT72V51336

• Choose from among the following memory density options:
IDT72V51336  Total Available Memory = 589,824 bits
IDT72V51346  Total Available Memory = 1,179,648 bits
IDT72V51356  Total Available Memory = 2,359,296 bits
• Configurable from 1 to 8 Queues
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per queue
• User programmable via serial port
• Default multi-queue device configurations
-IDT72V51336: 2,048 x 36 x 8Q
-IDT72V51346: 4,096 x 36 x 8Q
-IDT72V51356: 8,192 x 36 x 8Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Individual, Active queue flags (OV, FF, PAE, PAF, PR)
• Provides continuous PAE and PAF status of up to 8 Queues
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
- x36in to x36out
- x18in to x36out
- x9in to x36out
- x36in to x18out
- x36in to x9out
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available

The IDT72V51336 multi-queue flow-control devices are single chip within which anywhere between 1 and 8 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user.

Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.

The IDT72V51336 provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of all queues, including queues not selected for write or read operations, these flag busses provide an individual flag per queue. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide.

When Bus Matching of the IDT72V51336 is used the device ensures the logical transfer of data throughput in a Little Endian manner. for 36 bit input and 36 bit output port sizes. The Packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue.

The user of the IDT72V51336 has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 8, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. Both Master Reset and Partial Reset pins are provided on this device.

A Master Reset of the IDT72V51336 latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset. A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.