Features: • Choose from among the following memory density options: IDT72V51233 Total Available Memory = 589,824 bits IDT72V51243 Total Available Memory = 1,179,648 bits IDT72V51253 Total Available Memory = 2,359,296 bits• Configurable from 1 to 4 Queues̶...
IDT72V51243: Features: • Choose from among the following memory density options: IDT72V51233 Total Available Memory = 589,824 bits IDT72V51243 Total Available Memory = 1,179,648 bits IDT7...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol | Rating | Commercial | Unit |
VTERM | Terminal Voltage with respect to GND |
0.5 to +4.5 | V |
TSTG | Storage Temperature | 55 to +125 | °C |
IOUT | DC Output Current | 50 to +50 | mA |
The IDT72V51243 multi-queue flow-control devices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.
The IDT72V51243 provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 4 bit programmable flag busses are available, providing status of all queues, including queues not selected for write or read operations, these flag busses provide an individual flag per queue.
Bus Matching of the IDT72V51243 is available on this device, either port can be 9 bits or 18 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.
The user of the IDT72V51243 has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 4, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins of the IDT72V51243 are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset.
A JTAG test port of the IDT72V51243 is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.