Operating Temperature: 0°C ~ 70°C
Function: Synchronous
Mounting Type: Surface Mount
Voltage - Supply: 3.15 V ~ 3.45 V
Packaging: Tray
Manufacturer: IDT, Integrated Device Technology Inc
Access Time: 10ns
Series: 72V
Data Rate: 100MHz
Package / Case: 128-LQFP
Supplier Device Package: 128-TQFP (14x20)
Memory Size: 1.1M (32K x 36)
Features: •Memory storage capacity:
IDT72V368316,384 x 36
IDT72V369332,768 x 36
IDT72V3610365,536 x 36
•Clock frequencies up to 100 MHz (6.5 ns access time)
•Clocked FIFO buffering data from Port A to Port B
•IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
•Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
•Serial or parallel programming of partial flags
•Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte) Pinout
Specifications
| Symbol |
Rating |
Commercial |
Unit |
| VCC |
Supply Voltage Range |
0.5 to +4.6 |
V |
| VI(2) |
Input Voltage Range |
0.5 to VCC+0.5 |
V |
| VO(2) |
Output Voltage Range |
0.5 to VCC+0.5 |
V |
| IIK |
Input Clamp Current (VI< 0 or VI> VCC) |
±20 |
mA |
| IOK |
Output Clamp Current (VO= < 0 or VO> VCC) |
±50 |
mA |
| IOUT |
Continuous Output Current (VO= 0 to VCC) |
±50 |
mA |
| ICC |
Continuous Current Through VCC or GND |
±400 |
mA |
| TSTG |
Storage Temperature Range |
65 to 150 |
°C |
DescriptionThe IDT72V3693L10PF are designed to run off a 3.3V supply for exceptionally low power consumption. These devices are monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5 ns. The 16,384/32,768/65,536 x 36 dual-port SRAM FIFO buffersdata from Port A to Port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices of the IDT72V3693L10PF are synchronous (clocked) FIFOs, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or
Parameters: | Technical/Catalog Information | IDT72V3693L10PF |
| Vendor | IDT, Integrated Device Technology Inc |
| Category | Undefined Category |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | IDT72V3693L10PF
IDT72V3693L10PF
|
IDT72V3693L10PF Data Sheet
