Features: •Memory storage capacity: IDT72V3626256 x 36 x 2 IDT72V3636512 x 36 x 2 IDT72V36461,024 x 36 x 2•Clock frequencies up to 100 MHz (6.5ns access time)•Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C recei...
IDT72V3646: Features: •Memory storage capacity: IDT72V3626256 x 36 x 2 IDT72V3636512 x 36 x 2 IDT72V36461,024 x 36 x 2•Clock frequencies up to 100 MHz (6.5ns access time)•Two independent FIFOs...
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Symbol |
Rating |
Commercial |
Unit |
VCC |
Supply Voltage Range |
0.5 to +4.6 |
V |
VI(2) |
Input Voltage Range |
0.5 to VCC+0.5 |
V |
VO(2) |
Output Voltage Range |
0.5 to VCC+0.5 |
V |
IIK |
Input Clamp Current (VI< 0 or VI> VCC) |
±20 |
mA |
IOK |
Output Clamp Current(VO= < 0 or VO>VCC) |
±50 |
mA |
IOUT |
Continuous Output Current (VO= 0 to VCC) |
±50 |
mA |
ICC |
Continuous Current Through VCC or GND |
±400 |
mA |
TSTG |
Storage Temperature Range |
65 to 150 |
°C |
The IDT72V3646 are pin and functionally compatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic,high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual port SRAMFIFOs on board each chip buffer data between a bidirectional 36-bit bus (PortA) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices of the IDT72V3646 are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for