IDT72V3614

NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

The IDT72V3614 is a pin and functionally compatible version of the IDT723614, designed to run off a 3.3V supply for exceptionally low power consumption. This device is monolithic, high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns. The FIFO operates in IDT Standard mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data of the IDT72V3614 in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations. Three modes of byte-order swapping are possible with any bus size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths.