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IDT72V36103

Features: •Memory storage capacity: IDT72V368316,384 x 36IDT72V369332,768 x 36IDT72V3610365,536 x 36•Clock frequencies up to 100 MHz (6.5 ns access time)•Clocked FIFO buffering data from Port A to Port B•IDT Standard timing (using EFand FF) or First Word Fall Through Timing...

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SeekIC No. : 004372594 Detail

IDT72V36103: Features: •Memory storage capacity: IDT72V368316,384 x 36IDT72V369332,768 x 36IDT72V3610365,536 x 36•Clock frequencies up to 100 MHz (6.5 ns access time)•Clocked FIFO buffering dat...

IDT72V36103 Data Sheet

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Part Number:
IDT72V36103
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•Memory storage capacity:
  IDT72V368316,384 x 36
  IDT72V369332,768 x 36
  IDT72V3610365,536 x 36
•Clock frequencies up to 100 MHz (6.5 ns access time)
•Clocked FIFO buffering data from Port A to Port B
•IDT Standard timing (using EF and FF) or First Word Fall
  Through Timing (using OR and IR flag functions)
•Programmable Almost-Empty and Almost-Full flags; each has
  five default offsets (8, 16, 64, 256 and 1,024)
•Serial or parallel programming of partial flags
•Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
  (byte) 


Pinout

Connection Diagram


Specifications

Symbol Rating Commercial Unit
VCC Supply Voltage Range 0.5 to +4.6 V
VI(2) Input Voltage Range 0.5 to VCC+0.5 V
VO(2) Output Voltage Range 0.5 to VCC+0.5 V
IIK Input Clamp Current (VI< 0 or VI> VCC) ±20 mA
IOK Output Clamp Current (VO= < 0 or VO> VCC) ±50 mA
IOUT Continuous Output Current (VO= 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±400 mA
TSTG Storage Temperature Range 65 to 150 °C



Description

The IDT72V36103 are designed to run off a 3.3V supply for exceptionally low power consumption.  These devices are monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5 ns.  The 16,384/32,768/65,536 x 36 dual-port SRAM FIFO buffersdata from Port A to Port B.  FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.

The IDT72V36103 are  synchronous (clocked) FIFOs, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals.  The clocks for each port are independent of one another and can be asynchronous or




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