IDT72V265LA

` Choose among the following memory organizations:
    IDT72V255LA 8,192 x 18
    IDT72V265LA 16,384 x 18
` Pin-compatible with the IDT72V275/72V285 and IDT72V295/72V2105 SuperSync FIFOs
` Functionally compatible with the 5 Volt IDT72255/72265 family
` 10ns read/write cycle time (6.5ns access time)
` Fixed, low first word data latency time
` 5V input tolerant
` Auto power down minimizes standby power consumption
` Master Reset clears entire FIFO
` Partial Reset clears data, but retains programmable settings
` Retransmit operation with fixed, low first word datalatency time
` Empty, Full and Half-Full flags signal FIFO status
` Programmable Almost-Empty and Almost-Full flags, each flagcan default to one of two preselected offsets
` Program partial flags by either serial or parallel means
` Select IDT Standard timing (using EF and FF flags) or FirstWord Fall Through timing (using OR and IR flags)
` Output enable puts data outputs into high impedance state
` Easily expandable in depth and width
` Independent Read and Write clocks (permit reading andwriting simultaneously)
` Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin Slim Thin Quad Flat Pack (STQFP)
` High-performance submicron CMOS technology
` Industrial temperature range (40 to +85) is available

The IDT72V265LA are functionally compatible versions of theIDT72255/72265 designed to run off a 3.3V supply for very low powerconsumption. The IDT72V255LA/72V265LA are exceptionally deep, highspeed, CMOS First-In-First-Out (FIFO) memories with clocked read andwrite controls. These FIFOs offer numerous improvements over previousSuperSync FIFOs, including the following:
· The limitation of the frequency of one clock input with respect to the otherhas been removed. The Frequency Select pin (FS) has been removed,thus it is no longer necessary to select which of the two clock inputs, RCLKor WCLK, is running at the higher frequency.
· The period required by the retransmit operation is now fixed and short.
· The first word data latency period, from the time the first word is written to
an empty FIFO to the time it can be read, is now fixed and short. (The variableclock cycle counting delay associated with the latency period found onprevious SuperSync devices has been eliminated on this SuperSyncfamily.)
SuperSync FIFOs are particularly appropriate for networking, video,telecommunications, data communications and other applications that need tobuffer large amounts of data.
The input port of the IDT72V265LA is controlled by a Write Clock (WCLK) input and a Write Enable(WEN) input. Data is written into the FIFO on every rising edge of WCLK whenWEN is asserted. The output port is controlled by a Read Clock (RCLK) inputand Read Enable (REN) input. Data is read from the FIFO on every risingedge of RCLK when REN is asserted. An Output Enable (OE) input is providedfor three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0to fMAX with complete independence. There are no restrictions on thefrequency of one clock input with respect to the other.