IDT72V261LA

Features:

•  Choose among the following memory organizations:
    IDT72V261LA - 16,384 x 9
    IDT72V271LA - 32,768 x 9
•  Pin-compatible with the IDT72V281/72V291 and  IDT72V2101/
    72V2111SuperSync FIFOs
• Functionally compatible with the 5 Volt IDT72261/72271  family
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
•  5V input tolerant
•  Auto power down minimizes standby power consumption
•  Master Reset clears entire FIFO
•  Partial Reset clears data, but retains programmable settings
•  Retransmit operation with fixed, low first word data
    latency time
•  Empty, Full and Half-Full flags signal FIFO status
•  Programmable Almost-Empty and Almost-Full flags, each flag
    can default to one of two preselected offsets
•  Program partial flags by either serial or parallel means
•  Select IDT Standard timing (using EF and FF flags) or First
    Word Fall Through timing (using OR and IR flags)
•  Output enable puts data outputs into high impedance state
•  Easily expandable in depth and width
•  Independent Read and Write clocks (permit reading and writing
    simultaneously)
•  Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
    pin Slim Thin Quad Flat Pack (STQFP)
•  High-performance submicron CMOS technology
•  Industrial temperature range (40 °C to +85 °C) is available


Pinout




Specifications

Symbol	Rating	Com'l & Ind'l	Unit
VTERM	Terminal Voltage with respect to GND	0.5 to +5	V
TSTG	Storage Temperature	55 to +125	°C
IOUT	DC Output Current	50 to +50	mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.



Description

The IDT72V261LA/72V271LA are functionally compatible versions of the IDT72261/72271 designed to run off a 3.3V supply for very low power
consumption. The IDT72V261LA/72V271LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read andwrite controls. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the
other has been removed. The Frequency Select pin (FS) has been
removed, thus it is no longer necessary to select which of the two clock
inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short.
(The variable clock cycle counting delay associated with the latency
period found on previous SuperSync devices has been eliminated on
this SuperSync family.)

SuperSync FIFOs of the IDT72V261LA are particularly appropriate for network, video, teleommunications, data communications and other applications that need to uffer large amounts of data.

The input port of the IDT72V261LA is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs. The frequencies of both the RCLK and the WCLK signals may vary from to fMAX with complete independence. There are no restrictions on the equency of one clock input with respect to the other.

The IDT72V261LA have two modes of operation: In the IDT Standard Mode, the first word written to the FIFO is deposited into the memory array.  A read operation is required to access that word.  In the First Word Fall Through Mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required. The state of the FWFT/SI pin during Master Reset determines the mode in use.

The IDT72V261LA FIFOs have five flag functions, ,EF/,OR(Empty Flag or Output Ready), ,EE/,IR (Full Flag or Input Ready), and HF (Half-full Flag).  The ,EF and ,FF functions are selected in the IDT Standard Mode.

The  ,IR and ,EFOR functions of the IDT72V261LA are selected in the First Word Fall Through Mode.  ,IR indicates that the FIFO has free space to receive data.  ,OR indicates that data contained in the FIFO is available for reading.

,EFHF is a flag whose threshold is fixed at the half-way point in memory.  This flag can always be used  irrespective of mode.

,PAE, ,PAF of the IDT72V261LA can be programmed independantly to any point in memory.  They, also, can be used irrespective of mode. Programmable offsets determine the flag threshold and can be loaded by two methods: parallel or serial.  Two default offset settings are also provided, such that ,PAE can be set at
127 or 1023 locations from the empty boundary and the ,PAF threshold can be set at 127 or 1023 locations from the full boundary.  All these choices are made with,EFLD during Master Reset.

In the serial method, SEN together with LD are used to load the offset registers via the Serial Input (SI).  In the parallel method, ,WEN together with ,LD can be used to load the offset registers via Dn.  REN together with ,LD can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading is selected.

During Master Reset (,MRS) of the IDT72V261LA, the read and write pointers are set to the first location of the FIFO.  The FWFT line selects IDT Standard Mode or FWFT Mode.  The ,LD pin selects  one of two partial flag default settings (127 or 1023) and, also, serial or parallel programming. The flags are updated accordingly.

The Partial Reset ,(PRS) of the IDT72V261LA also sets the read and write pointers to the first location of the memory.  However, the mode setting, programming method, and partial flag offsets are not altered. The flags are updated accordingly. ,PRS is useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient.

The Retransmit function of the IDT72V261LA allows data to be reread from the FIFO more than once.  A LOW on the RT input during a rising RCLK edge initiates aretransmit operation by setting the read pointer to the first location of the memory array.

If, at any time, the FIFO of the IDT72V261LA is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power
down state.

The IDT72V261LA/72V271LA are fabricated using IDT's high speed submicron CMOS technology.