IDT72V18160

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
    damage to the device. This is a stress rating only and functional operation of the device at these
    or any other conditions above those indicated in the operational sections of this specification is not
    implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_CC terminal only.

The IDT V-III and Vx-III Multimedia FIFOs of the IDT72V18160 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with independent clocked read and write controls and high density offerings up to 1 Mbit.

Each FIFO of the IDT72V18160 has a data input port (Dn) and a data output port (Qn). The frequencies of both the RCLK (read port clock) and the WCLK (write port clock) signals may vary from 0 to fS_(MAX) with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.

These FIFOs of the IDT72V18160 have five flag pins, EF (Empty Flag), FF (Full Flag), HF (Halffull Flag), PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag).

PAE and PAF  of IDT72V18160 can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded with the serial interface to any user desired value or by default values. Eight default offset settings are provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and thePAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge WCLK, are used to load the offset registers via the Serial Input (SI).

During Master Reset (MRS) the read and write pointers are set to the first location of the FIFO.