IDT72V14165

NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

The IDT72V14165 devices are First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs have 16-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is written into the Multimedia FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock (RCLK) of the IDT72V14165 can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output.

These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full Flag (FF), and Half Full Flag (HF).