IDT72V11071

The IDT72V11071 are dual Multimedia FIFOs. The device is functionally equivalent to two independent FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B) of the IDT72V11071 has a 8-bit input data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7, QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA, WCLKB), and a Write Enable pin (WENA, WENB). Data is written into each of the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB) when the appropriate Write Enable pin is asserted.

The output port of each FIFO bank is controlled by its associated clock pin (RCLKA, RCLKB) and Read Enable pin (RENA, RENB). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA, FFB).

This FIFO of the IDT72V11071 is fabricated using IDT's high-performance submicron CMOS technology.