Features: • Choose from among the following memory organizations:
IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2
IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2
IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2
• User Selectable Quad / Dual Mode - Choose between two or
four independent FIFOs
• Quad Mode offers
- Eight discrete clock domain, (four write clocks & four read clocks)
- Four separate write ports, write data to four independent FIFOs
- 10-bit wide write ports
- Four separate read ports, read data from any of four independent FIFOs
- Independent set of status flags and control signals for each FIFO
• Dual Mode offers
- Four discrete clock domain, (two write clocks & two read clocks)
- Two separate write ports, write data to two independent FIFOs
- 10-bit/20-bit wide write ports
- Two separate read ports, read data from any of two independent FIFOs
- Independent set of status flags and control signals for each FIFO
- Bus-Matching on read and write port x10/x20
- Maximum depth of each FIFO is the same as in Quad Mode
FUNCTIONAL BLOCK DIAGRAMS
• Up to 200MHz operating frequency max, 4 Gbps per FIFO (SDR)
and 8 Gbps per FIFO (DDR)
• Double Data Rate, DDR is selectable, providing up to 400Mbps
bandwidth per data pin
• User selectable Single or Double Data Rate modes on both the
write port(s) and read port(s)
• All I/Os are LVTTL/ HSTL/ eHSTL user selectable
• 3.3V tolerant inputs in LVTTL mode
• ERCLK and EREN Echo outputs on all read ports
• Write enable WEN and Chip Select WCS input for each write port
• Read enable REN and Chip Select RCS input for each read port
• User Selectable IDT Standard mode (using EF and FF) or FWFT
mode (using IR and OR)
• Programmable Almost Empty and Almost Full flags per FIFO
• Dedicated Serial Port for flag offset programming
• Power Down pin minimizes power consumption
• 2.5V Supply Voltage
• Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
• IEEE 1149.1 compliant JTAG port provides boundary scan function
• Low Power, High Performance CMOS technology
• Industrial temperature range (-40°C to +85°C)Specifications
| Symbol |
Rating |
Com'l & Ind'l |
Unit |
| VTERM |
Terminal Voltage with respect to GND |
0.5 to +3.6(2) |
V |
| TSTG |
Storage Temperature |
55 to +125 |
°C |
| IOUT |
DC Output Current |
50 to +50 |
mA |
| TJ |
Maximum Junction Temperature |
+150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.DescriptionThe IDT72T54252 Quad/Dual TeraSync FIFO devices are ideal for many applications where data stream convergence and parallel buffering of multiple data paths are required. These applications may include communication systems such as data bandwidth aggregation, data acquisition systems and medical equipment, etc. The Quad/Dual FIFO allows the user to select either two or four individual internal FIFOs for operation. Each internal FIFO has its own discrete read and write clock, independent read and write enables, and separate status flags. The density of each FIFO is fixed.
If Quad mode of the IDT72T54252 is selected, there will be a total of eight clock domains, four read and four write clocks. Data can be written into any of the four write ports totally independent of any other port, and can be read out of any of the four read ports corresponding to their respective write port. Each port has its own control enables and status flags and is 10 bits wide. The device functions as four separate 10-bit wide FIFOs.
If Dual mode of the IDT72T54252 is selected, there will be a total of four clock domains, two read and two write clocks. Data can be written into any of the two write ports totally independent of any other port, and can be read out of any of the two read ports corresponding to their respective write port. Each port has its own controlenables and status flags. All input and output ports have bus-matching capabilities of x10 or x20 bits wide.
As typical with most IDT FIFOs of the IDT72T54252, two types of data transfer are available, IDT Standard mode and First Word Fall Through (FWFT) mode. This affects the device operation and also the flag outputs. The device provides eight flag outputs per input and output port. A dedicated Serial Clock is used for programming the flag offsets. This clock is also used for reading the offset values. The serial read and write operations are performed via the SCLK, FWFT/SI, SWEN, SREN, and SDO pins. The flag offsets can also be programmed using the JTAG port. If this option is selected, the SCLK, SWEN, and SREN pins must be disabled.
The Quad/Dual device of the IDT72T54252 is capable of up to 200MHz operation for all eight clock inputs, all clocks being totally independent of each other. Along with this high speed of operation the device ports are selectable between Single Data Rate, SDR mode and Double Data Rate, DDR mode. If Double Data Rate mode is selected, data can be written into or read out of a FIFO on every rising and falling edge of the respective clock. For example, if the write clock is running at 200MHz and the write ports is setup for DDR mode a data input pin has a bandwidth of 400 Mbps, so for a 20-bit wide bus a total bandwidth of 8 Gbps can be achieved.
All Read ports provide the user with a dedicated Echo Read Enable of the IDT72T54252, EREN and Echo Read Clock, ERCLK output. These outputs aid in high speed applications where synchronization of the input clock and data of receiving device is critical. Otherwise known as "Source Synchronous Clocking," the echo outputs provide tighter synchronization of the data transmitted from the FIFO and the read clock interfacing the FIFO outputs.
A Master Reset input of the IDT72T54252 is provided and all setup and configuration pins are latched with respect to a Master Reset pulse. For example, the mode of operation, bus-matching, and data rate are selected at Master Reset. A Partial Reset is provided for each internal FIFO. When a Partial Reset is performed on a FIFO the read and write pointers of that FIFO are reset to the first memory location. The flag offset values, timing modes, and initial configurations are retained.
The Quad/Dual device of the IDT72T54252 has the capability of operating its I/O at either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the IOSEL pin. The core supply voltage of the device, VCC is always 2.5V, however the output pins have a separate supply, VDDQ which can be 2.5V, 1.8V, or 1.5V.
The inputs of this device of the IDT72T54252 are 3.3V tolerant when VDDQ is set to 2.5V. The device also offers significant power savings, most notably achieved by the presence of a Power Down input, PD.
A JTAG test port of the IDT72T54252 is provided. The Quad/Dual device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
IDT72T54252 Data Sheet
