Features: • Choose from among the following memory density options:
IDT72T51543 Total Available Memory = 1,179,648 bits
IDT72T51553 Total Available Memory = 2,359,296 bits
• Configurable from 1 to 32 Queues
• Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
• Independent Read and Write access per queue
• User programmable via serial port
• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
• Default multi-queue device configurations
IDT72T51543 : 2,048 x 18 x 32Q
IDT72T51553 : 4,096 x 18 x 32Q
• 100% Bus Utilization, Read and Write on every clock cycle
• 200 MHz High speed operation (5ns cycle time)
• 3.6ns access time
• Echo Read Enable & Echo Read Clock Outputs
• Individual, Active queue flags (OV, FF, PAE, PAF)
• 8 bit parallel flag status on both read and write ports
• Shows PAE and PAF status of 8 Queues
• Direct or polled operation of flag status bus
• Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
• User Selectable Bus Matching Options:
x18in to x18out
x9in to x18out
x18in to x9out
x9in to x9out
• FWFT mode of operation on read port
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• Power Down Input provides additional power savings in HSTL
and eHSTL modes.
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is availableSpecifications
| Symbol |
Rating |
Commercial |
Unit |
| VTERM |
Terminal Voltage
with respect to GND |
0.5 to +3.6(2) |
V |
| TSTG |
Storage Temperature |
55 to +125 |
°C |
| IOUT |
DC Output Current |
50 to +50 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.DescriptionThe IDT72T51543 multi-queue flow-control devices are single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.
The IDT72T51543 provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode of bus operation provides the flag busses with all queues status.
Bus Matching of the IDT72T51543 is available on this device, either port can be 9 bits or 18 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.
The user of the IDT72T51543 has full flexibility configuring queues within the device, being able\ to program the total number of queues between 1 and 32, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins of the IDT72T51543 are provided on this device. A Master Reset latches in all configuration setup pins and must be performed before programming of the device can take place. A Partial Reset will reset the read and write pointers of an individual queue, provided that the queue is selected on both the write port and read port at the time of partial reset.
Echo Read Enable of the IDT72T51543, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the queue that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. Data read from the read port is available on the output bus with respect to EREN and ERCLK, this is very useful when data is being read at high speed.
The multi-queue flow-control device of the IDT72T51543 has the capability of operating its IO in either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the IOSEL input. The core supply voltage (VCC) to the multi-queue is always 2.5V, however the output levels can be set independently via a separate supply, VDDQ.
The IDT72T51543 also provide additional power savings via a Power Down Input. This input disables the write port data inputs when no write operations are required.
A JTAG test port of the IDT72T51543 is provided, here the multi-queue device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port\ and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.
IDT72T51543 Data Sheet
