IDT72T51268

The multi-queue DDR flow-control devices of the IDT72T51268 are ideal for many applications where functions such as data differentiation and parallel buffering of multiple data paths are required. These applications may include communication and networking systems such as routers, packet prioritization systems, data acquisition systems, imaging systems and medical equipment.

The IDT72T51268 multi-queue DDR flow-control devices are a single chip with four discrete FIFO queues available. All four queues have a fixed density and based on the bus matching arrangement can take the following memory arrangement: For the IDT72T51248, four queues each queue being 8,192 x40 or 16,384 x20 or 32,768 x10. For the IDT72T51258, four queues each queue being 16,384 x40 or 32,768 x20 or 65,536 x10. For the IDT72T51268, four queues each queue being 32,768 x40 or 65,536 x20 or 131,072 x10.

All queues within the device of the IDT72T51268 have a common data input bus (write port) and a common data output bus (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, the queue being address by the user via a two bit input select bus. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user via a two bit output select bus. Data write and read operations are totally independent of each other, a queue may be selected on the write port and a different queue selected on the read port, or both ports may select the same queue simultaneously.

Bus matching of the IDT72T51268 is provided on this device, the bus width selection is 'Global' which means that all four queues will have a fixed input width and a fixed output width. The write port bus width may be x10, x20 or x40 and the read port bus width may be x10, x20 or x40. When bus matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.

As is typical with most IDT FIFO's, two types of data transfer are available, IDT Standard mode and First word Fall Through (FWFT) Mode. This affects the device operation and also the flag outputs. The device provides four dedicated flag outputs for all internal Queue's. These flags are: Full/ Input Ready flag, Empty/ Output Ready flag, Programmable Almost Empty flag and Programmable Almost Full. The programmable flags have default values, but can also be set by the user to any point within the Queue depth. These programmable flags can also be configured by the user for either Synchronous or Asynchronous operation. The device also provides composite flags.

The multi-queue DDR device of the IDT72T51268 is capable of up to 200MHz operation on both write clock and read clock inputs, these clocks being totally independent of each other. Along with this high speed of operation the device ports are selectable between Single Data Rate, SDR mode and Double Data Rate, DDR mode. If Double Data Rate mode is selected data can be written into or read out of a Queue on every rising and falling edge of a respective clock. For example, if the write clock is running at 200MHz and the write port is set-up for DDR mode a data input pin has a bandwidth of 400Mbps, so for a 40 bit wide bus a total bandwidth of 16Gbps can be achieved.

The read port of the IDT72T51268 provides the user with a dedicated Echo Read Enable, EREN and Echo Read Clock, ERCLK output. These outputs are helpful in higher speed applications. Otherwise known as "Source Synchronous clocking" the echo outputs provide tighter synchronization of the data transmitted from the multiqueue flow-control device and the read clock being received at the downstream device.

A Master Reset input of the IDT72T51268 is provided and all set-up and configuration pins are latched with respect to a Master Reset. For example, the bus width requirements are selected at Master Reset. A Partial Reset is provided for each internal Queue. When a Partial Reset is performed on a Queue, the read and write pointers of that Queue only are reset to the first memory location. All other pointers remain the same.

The IDT72T51268 also has the capability of operating its I/O at either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, VREF input is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the IOSEL pin. The core supply voltage of the device, VCC is always 2.5V, however the output pins have a separate supply, VDDQ which can be 2.5V, 1.8V or 1.5V. The device also offers significant power savings in HSTL/eHSTL mode, most notably achieved by the presence of a Power Down input, PD.

A JTAG test port of the IDT72T51268 is provided. The multi-queue DDR device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The JTAG port can also be used to program the device set-up as described later in this document.