IDT72T18105

The IDT72T18105 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer several key user benefits:

• Flexible x18/x9 Bus-Matching on both read and write ports

• A user selectable MARK location for retransmit

• User selectable I/O structure for HSTL or LVTTL

• Asynchronous/Synchronous translation on the read or write ports

• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.

• High density offerings up to 9 Mbit

Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO of the IDT72T18105 has a data input port (D_n) and a data output port (Q_n), both of which can assume either a 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) pin during the Master Reset cycle.

The input port of the IDT72T18105 can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input.  Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW).

The output port of the IDT72T18105 can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input.  Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, also the RCS should be tied LOW and the OE input used to provide three-state control of the outputs, Qn.

The output port of the IDT72T18105 can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the RHSTL input during a master reset.

An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select (RCS) input is also provided, the RCS  input is synchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronous operation of the output port, RCS should be enabled, held LOW.

Echo Read Enable of the IDT72T18105, EREN  and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. Data read from the read port is available on the output bus with respect to EREN  and ERCLK, this is very useful when data is being read at high speed. The ERCLK and EREN outputs are non-functional when the Read port is setup for Asynchronous mode.

The frequencies of both the RCLK and the WCLK signals may vary from 0 to f_MAX with complete independence.  There are no restrictions on the frequency of the one clock input with respect to the other.

 There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In  IDT Standard mode of the IDT72T18105, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode,  the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access.  The state of the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next).  No external logic is required.

 These FIFOs of the IDT72T18105 have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag).  The EF and  FF functions are selected in IDT Standard mode.  The  IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in memory.  Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial.  Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary.  The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For  serial programming of the IDT72T18105, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI).  For parallel programming, WEN together with  LD on each rising edge of WCLK, are used to load the offset registers via Dn.  REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur:  the read and write pointers are set to the first location of the FIFO.  The FWFT pin selects IDT Standard mode or FWFT mode.

The Partial Reset (PRS) of the IDT72T18105 also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect.  PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the  PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags.

If asynchronous PAE/PAF configuration of the IDT72T18105 is selected,  the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration of the IDT72T18105 is selected , the  PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during Master Reset by the state of the Programmable Flag Mode (PFM) pin.

This IDT72T18105 includes a Retransmit from Mark feature that utilizes two control inputs, MARK and , RT  (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RT goes LOW, will reset the read pointer to this 'marked' location.