IDT72T1810

 Choose among the following memory organizations:
    IDT72T1845--2,048 x 18/4,096 x 9
    IDT72T1855 -- 4,096 x 18/8,192 x 9
    IDT72T1865 -- 8,192 x 18/16,384 x 9
    IDT72T1875 -- 16,384 x 18/32,768 x 9
    IDT72T1885 -- 32,768 x 18/65,536 x 9
    IDT72T1895 -- 65,536 x 18/131,072 x 9
    IDT72T18105 -- 131,072 x 18/262,144 x 9
    IDT72T18115 -- 262,144 x 18/524,288 x 9
    IDT72T18125 -- 524,288 x 18/1,048,576 x 9
 Up to 225 MHz Operation of Clocks
 User selectable HSTL/LVTTL Input and/or Output
 Read Enable & Read Clock Echo outputs aid high speed operation
 User selectable Asynchronous read and/or write port timing
 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
 3.3V Input tolerant
 Mark & Retransmit, resets read pointer to user marked position
 Write Chip Select (WCS) input enables/disables Write operations
 Read Chip Select (RCS) synchronous to RCLK
 Programmable Almost-Empty and Almost-Full flags, each flag candefault to one of eight preselected offsets
 Program programmable flags by either serial or parallel means
 Selectable synchronous/asynchronous timing modes for Almost-

The IDT72T1810 are exceptionally deep, extremely highspeed, CMOS First-In-First-Out (FIFO) memories with clocked read and writecontrols and a flexible Bus-Matching x18/x9 data flow. These FIFOs offerseveral key user benefits:
• Flexible x18/x9 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to anempty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs of the IDT72T1810 are particularly appropriate for network,video, telecommunications, datacommunications and other applications thatneed to buffer large amounts of data and match busses of unequal sizes.