Features: SpecificationsDescriptionThe IDT72851 are dual synchronous (clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins.Each of the two FIFOs (des...
IDT72851: Features: SpecificationsDescriptionThe IDT72851 are dual synchronous (clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/72221/72231/72241/72251 FIFOs in a single package wi...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
The IDT72851 are dual synchronous (clocked) FIFOs. The device is functionally equivalent to two IDT72201/72211/72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins.Each of the two FIFOs (designated FIFO A and FIFO B) contained in the IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0- DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA, WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB) when the appropriate write enable pins are asserted.The output port of each FIFO bank is controlled by its associated clock pin(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,RENB2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO for three-state output control.
It has many unique features of the IDT72851:The first one is it offers optimal combination of large capacity, high speed,design flexibility and small footprint. The second one is it is ideal for prioritization, bidirectional, and width expansion applications.The third one is 15 ns read/write cycle time for the IDT72851. The forth one is separate control lines and data lines for each FIFO. The fifth one is separate Empty, Full, Programmable Almost-Empty and Almost-Full flags for each FIFO.The sixth one is it enable puts output data lines in high-impedance state. The seventh one is space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin Quad Flatpack (STQFP),etc.
There are some absolute maximum ratings about the IDT72851.Terminal Voltage with Respect to GND(VTERM) is 0.5 to +7.0 V. StorageTemperature(TSTG) is 55°C to +125°C.DC Output Current(IOUT) is50 mA to +50 mA.Otherwise, there are also some recommended operating conidtions.Supply Voltage(Com'l & Ind'l)(VCC ) is 4.5 Vmin, 5.0V typ and 5.5 V max.Supply Voltage(Com'l & Ind'l)(GND) is 0 V.Input High Voltage(Com'l & Ind'l)(VIH) is 2.0 V min.Input Low Voltage(Com'l & Ind'l)(VIL) is 0.8 V max.Operating Temperature(TA ) is 0°C min and 70°C max(Commercial).Operating Temperature(TA) is 40°C to 85°C.