IDT72841

Features:

• The 72801 is equivalent to two 72201 256 x 9 FIFOs
• The 72811 is equivalent to two 72211 512 x 9 FIFOs
• The 72821 is equivalent to two 72221 1024 x 9 FIFOs
• The 72831 is equivalent to two 72231 2048 x 9 FIFOs
• The 72841 is equivalent to two 72241 4096 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
   design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
   applications
• 15 ns read/write cycle time FOR THE 72801/72811
• 20 ns read/write cycle time FOR THE 72821/72831/72841
• Separate control lines and data lines for each FIFO
• Separate empty, full, programmable almost-empty and
   almost-full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack (TQFP)
• Industrial temperature range (-40OC to +85OC) is available,
   tested to military electrical specifications


Pinout




Specifications

Symbol	Rating	Commercial	Unit
VTERM	Terminal Voltage with Respect to GND	0.5 to +70	V
TA	Operating Temperature	0 to +70
TBIAS	Temperature Under Bias	55 to +125
TSTG	Storage Temperature	55 to +125
IOUT	DC Output Current	50	mA

Description

IDT72841 are dual synchronous (clocked) FIFOs. The device is functionally equivalent to two 72201/72211/72221/72231/72241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the IDT72841 has a 9- bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each input port is controlled by a free-running clock(WCLKA, WCLKB), and two write enable pins ( WENA1 , WENA2, WENB1, WENB2). Data is written into each of the two arrays on every rising clock edge of the write clock (WCLKA WCLKB) when the appropriate write enable pins are asserted.

The output port of each FIFO bank of the IDT72841 is controlled by its associated clock pin (RCLKA, RCLKB) and two read enable pins ( RENA1, RENA2 , RENB1 , RENB2 ). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin ( OEA , OEB ) is provided on the read port of each FIFO for three-state output control .

Each of the two FIFOs of the IDT72841 has two fixed flags, empty ( EFA , EFB ) and full ( FFA , FFB ). Two programmable flags, almost-empty ( PAEA , PAEB ) and almost-full ( PAFA , PAFB ), are provided for each FIFO bank to improve memory utilization. If not programmed, the programmable flags default to empty+7 for PAEA and PAEB , and full-7 for PAFA and PAFB .

The IDT72841 architecture lends itself to many flexible configurations such as:
• 2-level priority data buffering
• Bidirectional operation
• Width expansion
• Depth expansion

This FIFO of the IDT72841 is fabricated using IDTs high-performance submicron CMOS technology.