IDT723672

Features:

• Memory storage capacity:
   IDT723652 2,048 x 36 x 2
   IDT723662 4,096 x 36 x 2
   IDT723672 8,192 x 36 x 2
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB may be asynchronous or coincident
   (simultaneous reading and writing of data on a single clock edge
   is permitted)
• Two independent clocked FIFOs buffering data in opposite directions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
   functions) or First Word Fall Through timing (using ORA, ORB, IRA
   and IRB flag functions)
• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
   120-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT723622/723632/723642
• Industrial temperature range (40°C to +85°C) is available


Pinout




Specifications

Symbol	Rating	Commercial	Unit
VCC	Supply Voltage Range	0.5 to +7.0	V
VI(2)	Input Voltage Range	0.5 to VCC+0.5	V
VO(2)	Output Voltage Range	0.5 to VCC+0.5	V
IIK	Input Clamp Current (VI < 0 or VI > VCC)	±20	mA
IOK	Output Clamp Current (VO = < 0 or VO > VCC)	±50	mA
IOUT	Continuous Output Current (VO = 0 to VCC)	±50	mA
ICC	Continuous Current Through VCC or GND	±400	mA
TSTG	Storage Temperature Range	65 to 150	°C

NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Description

The IDT723672 is a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 83MHz and have read access times as fast as 8ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored.