IDT723666 Selling Leads, Price trend, IDT723666 DataSheet download, circuit diagram from SeekIC.com

Features: •Memory storage capacity:IDT7236562,048 x 36 x 2IDT7236664,096 x 36 x 2IDT7236768,192 x 36 x 2•Clock frequencies up to 83 MHz (8ns access time)•Two independent FIFOs buffer data between one bidirectional36-bit port and two unidirectional 18-bit ports (Port C receivesand...

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SeekIC No. : 004372429 Detail

IDT723666: Features: •Memory storage capacity:IDT7236562,048 x 36 x 2IDT7236664,096 x 36 x 2IDT7236768,192 x 36 x 2•Clock frequencies up to 83 MHz (8ns access time)•Two independent FIFOs buff...

IDT723666 Data Sheet

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Part Number:: IDT723666
Supply Ability:: 5000

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1~5000

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Negotiable

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15 Days

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Upload time: 2025/3/12

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Product Details

Description

Features:

•Memory storage capacity:
IDT7236562,048 x 36 x 2
IDT7236664,096 x 36 x 2
IDT7236768,192 x 36 x 2
•Clock frequencies up to 83 MHz (8ns access time)
•Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
•18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C
•Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
•Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1024)
•Serial or parallel programming of partial flags
•Big- or Little-Endian format for word and byte bus sizes
•Loopback mode on Port A
•Retransmit Capability
•Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
•Mailbox bypass registers for each FIFO
•Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
•Auto power down minimizes power dissipation
•Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
•Pin compatible to the lower density parts, IDT723626/3636/3646
•Industrial temperature range (40°C to +85°C) is available

Pinout

Connection Diagram

Specifications

Symbol	Rating	Commercial	Unit
V_CC	Supply Voltage Range	0.5 to +7.0	V
V_I⁽²⁾	Input Voltage Range	0.5 to V_CC+0.5	V
V_O⁽²⁾	Output Voltage Range	0.5 to V_CC+0.5	V
I_IK	Input Clamp Current (V < 0 or V > VCC)	±20	mA
I_OK	Output Clamp Current (V_O= < 0 or V_O> V_CC)	±50	mA
I_OUT	Continuous Output Current (V_O= 0 to V_CC)	±50	mA
I_CC	Continuous Current Through V_CC or GND	±400	mA
T_STG	Storage Temperature Range	65 to 150	°C

Description

The IDT723666 is a monolithic, high-speed, low-power,CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can beread out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.

These devices of the IDT723666 are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for

IDT723666

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