IDT723624

The IDT723624 is a monolithic, high-speed, lowpower,CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read access times as fast as 8 ns.Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations.These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

It has many unique features of the IDT723624: The first one is serial or parallel programming of partial flags. The second one is port B bus sizing of 36-bits (long word), 18-bits (word) and 9-bits (byte).The third one is big- or Little-Endian format for word and byte bus sizes.The forth one is master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings. The fifth one is mailbox bypass registers for each FIFO. The sixth one is free-running CLKA and CLKB may be asynchronous or coincident(simultaneous reading and writing of data on a single clock edge is permitted),etc.

There are some absolute maximum ratings about the IDT723624. Supply Voltage Range(VCC)is 0.5 V to 7 V.Input Voltage Range(VI(2)) is 0.5 V to VCC+0.5 V.Output Voltage Range(VO(2)) is 0.5 V to VCC+0.5 V.Input Clamp Current(IIK)(VI < 0 or VI > VCC) is ±20 mA.Output Clamp Current(IOK) (VO = < 0 or VO > VCC) is ±50 mA.Continuous Output Current(IOUT)(VO = 0 to VCC) is ±50 mA.Continuous Current Through VCC or GND(ICC) is ±400 mA.Storage Temperature Range(TSTG) is65 to 150 °C.