IDT723614

The IDT723614 is a monolithic, high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags(almost-full and almost-empty) to indi-cate when a selected number of words is stored in memory.FIFO data on port B can be input and output in 36-bit, 18-bit,and 9-bit formats with a choice of big- or little-endian configu-rations. Three modes of byte-order swapping are possible with any bus size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired.Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths.

The IDT723614 is a clocked FIFO, which means each port employs a synchronous interface.All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals. The clocks for each port are independent of one another and can be asyn-