IDT723613

` Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge)
` 64 x 36 storage capacity FIFO buffering data from Port A to Port B
`Mailbox bypass registers in each direction
` Dynamic Port B bus sizing of 36 bits (long word), 18-bits (word), and 9 bits (byte)
`Selection of Big- or Little-Endian format for word and byte bus sizes
` Three modes of byte-order swapping on Port B
`Programmable Almost-Full and Almost-Empty flags
`Microprocessor interface control logic
` FF, AF flags synchronized by CLKA
`EF, AE flags synchronized by CLKB
`Passive parity checking on each Port
`Parity Generation can be selected for each Port
`Supports clock frequencies up to 67 MHz
` Fast access times of 10 ns
` Available in 132-pin quad flatpack (PQFP) or space-saving 120-pin thin quad flatpack (TQFP)
`Industrial temperature range (40 to +85) is available

The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro- nous (clocked) FIFO memory which supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO of the IDT723613 has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or Little-Endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively