IDT723612

The IDT723612 is a monolithic high-speed, low-power BiCMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths.

The IDT723612 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through
Note:
1. NC - No internal connection a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writesdata to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723612 is characterized for operation from 0°C to 70°C.