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IDT72285

Features: • Choose among the following memory organizations: IDT72275 - 32,768 x 18 IDT72285 - 65,536 x 18• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs• 10ns read/write cycle time (6.5ns access time)• Fixed, low first word data latency time• Auto power ...

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SeekIC No. : 004372404 Detail

IDT72285: Features: • Choose among the following memory organizations: IDT72275 - 32,768 x 18 IDT72285 - 65,536 x 18• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs• 10ns read/wr...

IDT72285 Data Sheet

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Part Number:
IDT72285
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Choose among the following memory organizations:
   IDT72275 - 32,768 x 18
   IDT72285 - 65,536 x 18
• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Retransmit operation with fixed, low first word data latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
   can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
   Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
   pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available


Pinout

Connection Diagram


Specifications

Symbol Rating Commercial Unit
VTERM Terminal Voltage with respect to GND 0.5 to +7 V
TSTG Storage Temperature 55 to +125 ° C
IOUT DC Output Current 50 to +50 mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.


Description

The IDT72285 are exceptionally deep, high speed, CMOS First-In- First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary    to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting    delay associated with the latency period found on previous SuperSync devices of the IDT72285 has been eliminated on this SuperSync family.)




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