IDT72255

• 8,192 x 18-bit storage capacity (IDT72255)
• 16,384 x 18-bit storage capacity (IDT72265)
• 10ns read/write cycle time (8ns access time)
• Retransmit Capability
• Auto power down reduces power consumption
• Master Reset clears entire FIFO, Partial Reset clearsdata, but retains programmable settings
• Empty, Full and Half-full flags signal FIFO status
• Programmable Almost Empty and Almost Full flags, eachflag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FFflags) orFirst Word Fall Through timing (using OR and IR flags)
• Easily expandable in depth and width
• Independent read and write clocks (permit simultaneousreading and writing with one clock signal)
• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-pin Slim Thin Quad Flat Pack (STQFP) and the 68-pinPin Grid Array (PGA)
• Output enable puts data outputs into high impedance
• High-performance submicron CMOS technology
• Industrial temperature range (-40oC to +85oC) is available,tested to military electrical specifications

The IDT72255/72265 are monolithic, CMOS, high capacity,high speed, low power First-In, First-Out (FIFO) memorieswith clocked read and write controls. These FIFOs are applicablefor a wide variety of data buffering needs, such as opticaldisk controllers, local area networks (LANs), and inter-processorcommunication.

Both FIFOs of the IDT72255 have an 18-bit input port (Dn) and an 18-bitoutput port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN). Data iswritten into the synchronous FIFO on every clock when WENis asserted. The output port is controlled by another clock pin(RCLK) and enable pin (REN). The read clock can be tied tothe write clock for single clock operation or the two clocks canrun asynchronously for dual clock operation. An output enablepin (OE) is provided on the read port for three-state control ofthe outputs.

The IDT72255/72265 have two modes of operation: In theIDT Standard Mode, the first word written to the FIFO isdeposited into the memory array. A read operation is requiredto access that word. In the First Word Fall Through Mode(FWFT), the first word written to an empty FIFO appearsautomatically on the outputs, no read operation required. Thestate of the FWFT/SI pin during Master Reset determines themode in use.