Features: • 25ns parallel port access time, 35ns cycle time• 45MHz serial output shift rate• Wide x16 organization offering easy expansion• Low power consumption (50mA typical)• Least/Most Significant Bit first read selected by asserting the FL/DIR pin• Four mem...
IDT72125: Features: • 25ns parallel port access time, 35ns cycle time• 45MHz serial output shift rate• Wide x16 organization offering easy expansion• Low power consumption (50mA typica...
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Symbol |
Rating |
Commercial |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
0.5 to + 7.0 |
V |
TA |
Operating Temperature |
0 to +70 |
°C |
TBIAS |
Temperature Under Bias |
55 to +125 |
°C |
TSTG |
Storage Temperature |
55 to + 125 |
°C |
IOUT |
DC Output Current |
50 |
mA |
The IDT72125 are very high-speed, lowpower, dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively.
The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/tape controller applications.
Expansion in width and depth can be achieved using multiple chips. IDT's unique serial expansion logic makes this possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset.
Monitoring the FIFO is eased by the availability of four status flags: Empty, Full, Half-Full and Almost-Empty/Almost- Full. The Full and Empty flags prevent any FIFO data overflow or underflow conditions. The Half-Full Flag is available in both single and expansion mode configurations. The Almost-Empty/ Almost-Full Flag is available only in a single device mode. The IDT72125 are fabricated using IDT's leading edge, submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of Mil- STD-883, Class B.