IDT71V633

The IDT71V633 is a 3.3V high-speed 2,097,152-bit (2-Mbit) SRAMorganized as 64K x 32 with full support of various processor interfacesncluding the Pentium™ and PowerPC™. The flow-through burst archi-tecture provides cost-effective 2-1-1-1 performance for processors up to50 MHz.

The IDT71V633 SRAM contains write, data-input, address and controlregisters. There are no registers in the data output path (flow-througharchitecture). Internal logic allows the SRAM to generate a self-timed writebased upon a decision which can be left until the extreme end of the writecycle.

The burst mode feature offers the highest level of performance to the ystem designer, as the IDT71V633 can provide four cycles of data for  single address presented to the SRAM. An internal burst address ounter accepts the first cycle address from the processor, initiating the  ccess sequence. The first cycle of output data will flow-through from therray after a clock-to-data access time delay from the rising clock edge of he same cycle. If burst mode operation is selected (ADV=LOW), the ubsequent three cycles of output data will be available to the user on the ext three rising clock edges. The order of these three addresses will be efined by the internal burst counter and theLBO input pin.

The IDT71V633 SRAM utilizes IDT's high-performance 3.3V CMOS rocess, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin hin plastic quad flatpack (TQFP).