IDT71V632

The IDT71V632 is a 3.3V high-speed 1,048,576-bit CacheRAMorganized as 32K x 32 with full support of the Pentium™ and Pprocessor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to 100 MHz.

The IDT71V632 CacheRAM contains write, data, address, and control registers. Internal logic allows the CacheRAM to generate a selftimed write based upon a decision which can be left until the extreme end of the write cycle.

The burst mode feature offers the highest level of performance to the system designer, as the IDT71V632 can provide four cycles of data for a single address presented to the CacheRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin.

The IDT71V632 CacheRAM utilizes IDT's high-performance, highvolume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density in both desktop and notebook applications.