IDT71V509

The IDT71V509 is a 3.3V high-speed 1,024,576-bit synchronous RAM organized as 128K x 8. It is designed to liminate dead cycles when turning the bus around between eads and writes, or writes and reads. Thus, it has been given  he name ZBT™, or Zero Bus Turnaround™.

Addresses and control signals are applied to the SRAM during one clock cycle, and one clock cycle later its associated
data cycle occurs, be it read or write.

The IDT71V509 contains data, address, and control signal egisters. Output Enable is the only asynchronous signal, and an be used to disable the output at any time.

A Clock Enable (CEN) pin allows operation of the IDT71V509 o be suspended as long as necessary. All synchronous nputs are ignored when CEN is high. A Chip Select (CS) pin llows the user to deselect the device when desired. If CS is  igh, no new memory operation is initiated, but any pending ata transfers (reads and writes) will still be completed.

The IDT71V509 utilizes IDT's high-performance 3.3V CMOS rocess, and is packaged in a JEDEC Standard 400-mil 44- ead small outline J-lead plastic package (SOJ) for high board ensity.