IDT71V3557SA

The IDT71V3557SA are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write.

The IDT71V3557SA contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE₁, CE₂, CE₂) of the IDT71V3557SA that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after chip is deselected or a write is initiated.

The IDT71V3557SA have an on-chip burst counter. In the burst mode, the IDT71V3557/59 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by theLBO input pin. TheLBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V3557SA SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA).