IDT71V2556S

128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 200 MHz(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and readcycles
Internally synchronized output buffer enable eliminates theneed to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and controlsignal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW BW 1 - BW BW 4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
Optional - Boundary Scan JTAG Interface (IEEE 1149.1complaint)
Packaged in a JEDEC standard 100-pin plastic thin quadflatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitchball grid array (fBGA)

The IDT71V2556S are 3.3V high-speed 4,718,592-bit (4.5 Megabit)synchronous SRAMS. They are designed to eliminate dead bus cycleswhen turning the bus around between reads and writes, or writes andreads. Thus, they have been given the name ZBTTM, or Zero BusTurnaround.

Address and control signals are applied to the SRAM during one clockcycle, and two cycles later the associated data cycle occurs, be it reador write.

The IDT71V2556S contain data I/O, address and control signalregisters. Output enable is the only asynchronous signal and can be usedto disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2556S tobe suspended as long as necessary. All synchronous inputs are ignoredwhen (CEN) is high and the internal device registers will hold their previousvalues.

There are three chip enable pins (CE 1, CE2, CE 2) that allow the userto deselect the IDT71V2556S when desired. If any one of these three are notasserted when ADV/LD is low, no new memory operation can be initiated.However, any pending data transfers (reads or writes) will be completed.The data bus will tri-state two cycles after chip is deselected or a write isinitiated.

The IDT71V2556S has an on-chip burst counter. In the burst mode,the IDT71V2556/58 can provide four cycles of data for a single addresspresented to the SRAM. The order of the burst sequence is defined by theLBO input pin. The LBO pin selects between linear and interleaved burstsequence. The ADV/LD signal is used to load a new external address(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =HIGH).

The IDT71V2556S SRAMs utilize IDT's latest high-performanceCMOS process and are packaged in a JEDEC standard 14mm x 20mm100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array(BGA) and a 165 fine pitch ball grid array (fBGA).