IDT71T75602

512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 225 MHz
  (3.0 ns Clock-to-Data Access)

ZBT^TM  Feature - No dead cycles between write and read

   cycles
Internally synchronized output buffer enable eliminates the
   need to control OE

Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
   signal registers for fullypipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW₁ - BW₄) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V_DDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18  Megabit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, orwrites and reads. Thus, they have been given the name ZBT^TM , or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71T75602/802 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.A Clock Enable CENpin allows operation of the IDT71T75602/802 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE₁, CE₂, CE₂) of the IDT71T75602 that allow the user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated.