IDT71P72604

Features:

18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
 Separate, Independent Read and Write Data Ports
       - Supports concurrent transactions
 Dual Echo Clock Output
 2-Word Burst on all SRAM accesses
 DDR (Double Data Rate) Multiplexed Address Bus
      - One Read and One Write request per clock cycle
 DDR (Double Data Rate) Data Buses
      - Two word burst data per clock on each port
      - Four word transfers per clock cycle (2 word
         bursts on 2 ports)
Depth expansion through Control Logic
 HSTL (1.5V) inputs that can be scaled to receive signals
    from 1.4V to 1.9V.
 Scalable output drivers
      - Can drive HSTL, 1.8V TTL or any voltage level
         from 1.4V to 1.9V.
      - Output Impedance adjustable from 35 ohms to 70
         ohms
1.8V Core Voltage (VDD)
 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface


Specifications

Symbol	Rating	Value	Unit
VTERM	Supply Voltage on VDD with Respect to GND	0.5 to +2.9	V
VTERM	Supply Voltage on VDDQ with Respect to GND	0.5 to VDD +0.3	V
VTERM	Voltage on Input terminals with respect to GND.	0.5 to VDD +0.3	V
VTERM	Voltage on Output and I/O te rm inals with respect to GND.	-0.5 to VDDQ +0.3	V
TBIAS	Temperature Under Bias	55 to +125	°C
TSTG	Storage Temperature	65 to +150	°C
IOUT	Continuous Current into Outputs	± 20	mA

Description

The IDT71P72604 Burst of two SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports.  This scheme allows simultaneous read and write access for the maximum device throughput, with two data items passed with each read or write.   Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance.  Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds.  Considering that QDRII allows clock speeds  in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications.

Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses.  All buses
associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds.  The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.

The IDT71P72604 has a single DDR address bus with multiplexed read and write addresses.  All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle.  The read and write enables are received on the first half of
the clock cycle.  The byte and nibble write signals are received on both halves of the clock cycle simultaneously with the data they are controlling
on the data input bus.

The IDT71P72604 has echo clocks, which provide the user with a clock  The device is capable of sustaining full bandwidth on both the input and output ports simultaneously.  All data is in two word bursts, with addressing capability to the burst level.

that is precisely timed to the data output, and tuned with matching impedance and signal quality.  The user can use the echo clock for downstream clocking of the data.  Echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture.  Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source.

 All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface.  The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary.  The IDT71P72604 has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V V_DD.  The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines.