IDT71F432

NOTE: 3555 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The IDT71F432 MCache is a high-performance, low-power replacement for standard 32K x 32 pipelined burst SRAM (PBSRM) in cache applications. The 71F432 is built using IDT's Fusion Memory technology, which combines the performance of SRAM with the cost structure of DRAM. It isfundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation of the memory. These additional features are defined so that 71F432 compatible system controllers and properly implemented PC boards can work transparently with either the IDT71F432 or PBSRAM in cache memory applications.

Six pins, identified as No Connect (NC) on the standard PBSRAM specifications, are used to support 71F432 operation. These pins are 5V supply (2), host bus W/R#, RESET# and two proprietary functions labeled F0 and F1. When using standard PBSRAM, these pins have no effect and the associated functions in the 71F432-compatible chipset are not
activated.

The IDT71F432 supports PBSRAM operating modes, including burst read (3-1-1-1), burst write (3-1-1-1) and pipelined burst read or write (3-1-1-1-1-1...). As with all DRAM devices, refresh is required. The memory is not accessible during the refresh interval. Refresh occupies 0.5% of the clock cycles, resulting in a system performance reduction of less than 0.1%.