Features: •16K x 15 Configuration
- 12 TAG Bits
- 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
•Match output uses Valid bit to qualify MATCH output
•High-Speed Address-to-Match comparison times
- 8/9/10/12ns over commercial temperature range
•TA circuitry included inside the Cache-Tag for highest speed operation
•Asynchronous Read/Match operation with Synchronous Write and Reset operation
•Separate WE for the TAG bits and the Status bits
•Separate OE for the TAG bits, the Status bits, and TA
•Synchronous RESET pin for invalidation of all Tag entries
•Dual Chip selects for easy depth expansion with no performance degredation
•I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins
•PWRDN pin to place device in low-power mode
•Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP)Pinout
Specifications
|
Symbol |
Rating |
Value |
Unit |
|
VTERM |
Terminal Voltage
with Respect to GND |
-0.5 to +70(2) |
V |
|
TA |
Operating Temperature |
-0 to +70 |
oC |
|
TBIAS |
Temperature Under Bias |
-65 to +135 |
oC |
|
TSTG |
Storage Temperature |
-65 to +150 |
oC |
|
PT |
Power Dissipation |
1.7 |
W |
|
IOUT |
DC Output Current |
20 |
mA |
DescriptionThe IDT71216 is a 245,760-bit Cache Tag StaticRAM,organized 16K x 15 and designed to support PowerPC and other RISC processors at bus speeds up to 66MHz. There are twelve common I/O TAG bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored TAG bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address.
This high-speed MATCH signal, with t ADM as fast as 8ns,provides the fastest possible enabling of secondary cache accesses.
The three separate I/O status bits (VLD, DTY, and WT) can be configured for either dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC LOW, the status bits are defined and used internally by the device,allowing easier determination of the validity and use of the given Tag data. SFUNC HIGH releases the defined internal status bit usage and control, allowing the user to configure the status bit information to fit his system needs. A synchronous RESET pin, when held LOW at a rising clock edge, will reset all status bits in the array for easy invalidation of all Tag addresses.
The IDT71216 also provides the option for Transfer Ac-knowledge (TA) generation within the cache tag itself, based upon MATCH, VLD bit, WT bit, and external inputs provided by the user. This can significantly simplify cache controller logic and minimize cache decision time. Match and Read operations are both asynchronous in order to provide the fastest access times possible, while Write operations are synchronous for ease of system timing.
The IDT71216 uses a 5V power supply on Vcc, with separate VCCQ pins provided for the outputs to offer compli-ance with both 5.0V TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby mode to reduce power consumption by 90%, providing significant system power savings.
The IDT71216 is fabricated using IDT's high-performance, high-reliability BiCMOS technology and is offered in a space- saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
IDT71216 Data Sheet
