Features: ` True Dual-Ported memory cells which allow simultaneous access of the same memory location
` High-speed clock to data access
Commercial: 6/7.5/9/12ns (max.)
Industrial: 9ns (max.)
` Low-power operation
IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
` Flow-Through or Pipelined output mode on either port via the FT/PIPE pins
` Dual chip enables allow for depth expansion without additional logic
` Counter enable and reset features
` Full synchronous operation on both ports
3.5ns setup to clock and 0ns hold on all control, data, and address inputs
Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
10ns cycle time, 100MHz operation in Pipelined output mode
` LVTTL- compatible, single 3.3V (±0.3V) power supply
` Industrial temperature range (40°C to +85°C) is available for selected speeds
` Available in a 100-pin Thin Quad Flatpack (TQFP)
Pinout
Specifications
| Symbol |
Rating |
Commercial
& Industrial
|
Unit |
| VTERM(2) |
Terminal Voltage with Respect to GND |
-0.5 to +4.6 |
V |
| TBIAS |
Temperature Under Bias |
55 to +125 |
|
| TSTG |
Storage Temperature |
65 to +150 |
|
| TJN |
Junction Temperature |
+150 |
|
| IOUT |
DC Output Current |
50 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to 20mA for the period of VTERM VDD + 0.3V.
3. Ambient Temperature Under Bias. Chip Deselected.DescriptionThe IDT70V9199L is a high-speed128K x9/x8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on ontrol, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.
With an input data register, the IDT70V9199L has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
IDT70V9199L Data Sheet
