IDT70V7599S

Features: ` 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture 64 independent 2K x 36 banks 4 megabits of memory on chip` Bank access controlled via bank address pins` High-speed data access Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.) Industrial: 3.6ns (166...

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IDT70V7599S Picture
SeekIC No. : 004372152 Detail

IDT70V7599S: Features: ` 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture 64 independent 2K x 36 banks 4 megabits of memory on chip` Bank access controlled via bank address pins` High-speed ...

floor Price/Ceiling Price

Part Number:
IDT70V7599S
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Features:

` 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture
   64 independent 2K x 36 banks
   4 megabits of memory on chip
` Bank access controlled via bank address pins
` High-speed data access
   Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.)
   Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
` Selectable Pipelined or Flow-Through output mode
` Counter enable and repeat features
` Dual chip enables allow for depth expansion without additional logic
` Full synchronous operation on both ports
   5ns cycle time, 200MHz operation (14Gbps bandwidth)
   Fast 3.4ns clock to data out
   1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz
   Data input, address, byte enable and control registers
   Self-timed write allows fast cycle time
` Separate byte controls for multiplexed bus and bus matching compatibility
` LVTTL- compatible, 3.3V (±150mV) power supply for core
` LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
` Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz
` Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA)
`Supports JTAG features compliant with IEEE 1149.1



Pinout

  Connection Diagram


Specifications

Symbol Rating
Commercial
& Industrial
Unit
VTERM(2) Terminal Voltage with Respect to GND
0.5 to +4.6
V
TBIAS Temperature Under Bias
55 to +125
TSTG Storage Temperature
60 to +150
IOUT DC Output Current
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to   20mA for the period of VTERMVDD + 150mV.



Description

The IDT70V7599S is a high-speed 128Kx36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7599S has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also acilitate depth expansion.

The IDT70V7599S can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.




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