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IDT70V631S

Features: ` True Dual-Port memory cells which allow simultaneous ccess of the same memory location` High-speed access Commercial: 10/12/15ns (max.) Industrial: 12ns (max.)` Dual chip enables allow for depth expansion without external logic` IDT70V631 easily expands data bus width to 36 bits or mo...

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IDT70V631S: Features: ` True Dual-Port memory cells which allow simultaneous ccess of the same memory location` High-speed access Commercial: 10/12/15ns (max.) Industrial: 12ns (max.)` Dual chip enables allow ...

IDT70V631S Data Sheet

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Part Number:
IDT70V631S
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` True Dual-Port memory cells which allow simultaneous ccess of the same memory location
` High-speed access
  Commercial: 10/12/15ns (max.)
   Industrial: 12ns (max.)
` Dual chip enables allow for depth expansion without external logic
` IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more
than one device
` M/S = VIH for BUSY output flag on Master,M/S = VIL forBUSY input on Slave
` Busy and Interrupt Flags
` On-chip port arbitration logic
` Full on-chip hardware support of semaphore signaling between ports
` Fully asynchronous operation from either port
` Separate byte controls for multiplexed bus and bus matching compatibility
` Supports JTAG features compliant to IEEE 1149.1
    -Due to limited pin count, JTAG is not supported on the 128-pin TQFP package.
` LVTTL-compatible, single 3.3V (±150mV) power supply for  core
` LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power  supply for I/Os and control signals on each port
` Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array
` Industrial temperature range (40°C to +85°C) is available for selected speeds


Pinout

Connection Diagram


Specifications

Symbol Rating

Commercial
& Industrial
Unit
VTERM(2) Terminal Voltage with Respect to GND
-0.5 to +4.6
V
TBIAS Temperature Under Bias
55 to +125
TSTG Storage Temperature
65 to +150
IOUT DC Output Current
50
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or4ns maximum, and is limited to  20mA for the period of VTERM VDD + 150mV.


Description

The IDT70V631S is a high-speed 256K x 18 Asynchronous Dual-PortStatic RAM. The IDT70V631 is designed to be used as a stand-alone4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory systemapplications results in full-speed, error-free operation without the need foradditional discrete logic.

This IDT70V631S provides two independent ports with separate control,address, and I/O pins that permit independent, asynchronous access forreads or writes to any location in memory. An automatic power downfeature controlled by the chip enables (either CE0 or CE1) permit theon-chip circuitry of each port to enter a very low standby power mode.

The IDT70V631S can support an operating voltage of either 3.3V or 2.5Von one or both ports, controlled by the OPT pins. The power supply forthe core of the device (VDD) remains at 3.3V.




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