Features: True four-ported memory cells which allow simultaneousaccess of the same memory locationSynchronous Pipelined device 64/32K x 18 organizationPipelined output mode allows fast 200MHz operationHigh Bandwidth up to 14 Gbps (200MHz x 18 bits wide x4 ports)LVTTL I/O interfaceHigh-speed clock ...
IDT70V5378: Features: True four-ported memory cells which allow simultaneousaccess of the same memory locationSynchronous Pipelined device 64/32K x 18 organizationPipelined output mode allows fast 200MHz operat...
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True four-ported memory cells which allow simultaneousaccess of the same memory location
Synchronous Pipelined device 64/32K x 18 organization
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x4 ports)
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
Counter wrap-around control
Internal mask register controls counter wrap-around
Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Symbol |
Ratin |
Commercial & Industrial |
Unit |
VTERM(2) |
Terminal Voltagewith Respect to GN |
-0.5 to +4.6 |
V |
TBIAS(3) |
Temperature Under Bias |
-55 to +125 |
|
TSTG |
Storage Temperature |
-65 to +150 |
|
TJN |
Junction Temperature |
+150 |
|
IOUT |
DC Output Current |
50 |
mA |
The IDT70V5378 is a high-speed 64/32Kx18 bitsynchronous FourPort RAM. The memory array utilizesFourPort memory cells to allow simultaneous access ofany address from all four ports. Registers on control, data,and address inputs provide minimal setup and hold times.The timing latitude provided by this approach allows sys-tems to be designed with very short cycle times.
With an input data register and integrated burstcounters, the 70V5388/78 has been optimized for applica-tionshaving unidirectional or bi-directional data flow inbursts. An automatic power down feature, controlled by CE 0and CE1, permits the on-chip circuitry of each port to entera very low standby power mode.
The IDT70V5378 provides a wide range of func-tions specially designed to facilitate system operations.These include full-boundary, maskable address counterswith associated interrupts for each port, mailbox interruptflags on each port to facilitate inter-port communications,Memory Built-In Self-Test (MBIST), JTAG support and anasynchronous Master Reset to simplify device initializa-tion. In addition, the address lines of the IDT70V5378 have been set up as I/Opins, to permit the support of CNTRD (the ability to output thecurrent value of the internal address counter on the addresslines) and MKRD (the ability to output the current value of thecounter mask register). For specific details on the deviceoperation, please refer to the Functional Description andsubsequent explanatory sections, beginning on page 21.