IDT70T6331S

True Dual-Port memory cells which allow simultaneous access of the same memory location
High-speed access
Commercial: 8/10/12/15ns (max.)
Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write cycles
Dual chip enables allow for depth expansion without external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
Full hardware support of semaphore signaling between ports on-chip
On-chip port arbitration logic
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array
Industrial temperature range (40°C to +85°C) is available for selected speeds

The IDT70T6331S is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T6331S is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS- TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This IDT70T6331S provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the  chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T6331S has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high perfor- mance levels.

The IDT70T6331S can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) remains at 2.5V.