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IDT70T3399S

Features: True Dual-Port memory cells which allow simultaneous access of the same memory locationHigh-speed data access Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.)Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)Selectable Pipelined or Flow-Through output modeCounter enable and re...

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SeekIC No. : 004372079 Detail

IDT70T3399S: Features: True Dual-Port memory cells which allow simultaneous access of the same memory locationHigh-speed data access Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.)Industrial: 3.6ns...

IDT70T3399S Data Sheet

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Part Number:
IDT70T3399S
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

True Dual-Port memory cells which allow simultaneous access of the same memory location
High-speed data access Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.)
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports 5ns cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock to data out 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz Data input, address, byte enable and control registers Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
Industrial temperature range (-40 to +85) is available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG, Collision Detection and Interrupt are not supported on the 144-pin TQFP package


Pinout

Connection Diagram


Specifications

Symbol Rating Commercial
& Industrial		 Unit
VTERM
(VDD)		 VDD Terminal Voltage
with Respect to GND		 -0.5 to 3.6 V
VTERM(2)
(VDDQ)		 VDDQ Terminal Voltage
with Respect to GND		 -0.3 to VDDQ + 0.3 V
VTERM(2)
(INPUTS and I/Os)		 Input and I/O Terminal
Voltage with Respect to GND		 -0.3 to VDDQ + 0.3 V
TBIAS(3) Temperature Under Bias -55 to +125
TSTG Storage Temperature -65 to +150
TJN Junction Temperature +150
IOUT(For VDDQ = 3.3V) DC Output Current 50 mA
IOUT(For VDDQ = 2.5V) DC Output Current 40 mA



Description

The IDT70T3399S is a high-speed 512/256/128k x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3399S has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE 0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70T3399S can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.




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